Set No: 1 R10
III B.Tech. I Semester Regular Examinations, November/December - 2012DIGITAL IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 Hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Design a CMOS transistor circuit for 2 input NAND gate with the help of the function table explain the circuit.
(b) Explain the CMOS gate circuit behavior with resistive load.
2. (a) Compare the CMOS, TTL, ECL logic families with respect to logic levels, power consumption, propagation delay and noise margin.
(b) Explain the sinking and sourcing currents in TTL.
3. (a) Design a excess-3 to BCD code converter and draw the truth table and logic diagram for it.
(b) Write a VHDL code for BCD to 7 segment display.
4. (a) Design a 4-bit carry look ahead adder using gates and draw the dataflow VHDL program.
(b) Design a barrel shifter for 8-bit using the three control inputs.
5. (a) Discuss the steps for the design of synchronoussequential circuit.
(b) (i) How many number of flip flops are needed tobuild a binary counter that counts from 0 to 1023.
(ii) Determine the frequency at the output of last (MSB) flip flop for an input clock frequency.
(iii) If the output is initially at zero, what willhold after 2060 clock pulses.
(iv) Draw the block diagram for the above said counter using TTL.
6. (a) Design a 4-bit LFSR counter.
(b) Explain how to perform serial to parallel conversion using 74x166.
7. (a) What is PLA? Explain the PLA with the help of the block diagram.
(b) Implement the following multi Boolean function using 3x4x2 PLA.
F1(A,B,C)= Σm(0,1,3,5)
F2=(A,B,C)= Σm(3,5,7)
8. Write a short notes on
(a) Two Dimensional decoding.
(b) Static RAM
*****
Set No: 2 R10
III B.Tech. I Semester Regular Examinations, November/December - 2012DIGITAL IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 Hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
*****
(b) Explain the dynamic electrical behavior of the CMOS.
2. (a)Explain how to interface CMOS with TTL logic.
(b) What is the drawback of open collector output in TTL. Compare it with the TOTEM PLOE output.
3. (a) Implement the 32 input to 5 output priority encoder using the four 74LS148 & gates.
(b) Write a VHDL code for 2 to 4 binary decoder.
4. (a) Explain the floating point encoder.
(b) Design a 4-bit parallel adder using the full adder.
5. (a)Explain the conversion from T flip flop to D- flip flop.
(b) Design a 4-bit up/down ripple counter with a Control for up/down counting.
6. (a) Explain the function of universal shift register and draw the logic diagram.
(b) Explain the 4-bit serial in parallel out shift register.
7. (a) Implement the following Boolean function using PROM
F1 (A, B) = Σm (1,2)
F2= (A, B) = Σm (0,1,3)
(b) Differentiate between PLA and PAL.
8. Write a short notes on
a) SRAM timing.
b) Dynamic RAM.
Set No: 3 R10
III B.Tech. I Semester Regular Examinations, November/December - 2012DIGITAL IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 Hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
*****
1. (a) Explain the CMOS logic families.
(b) Design a NOR gate using CMOS? Verify the truth table with necessary sketches
2. (a) What is wired AND connection in TTL? Explain.
(b) What is ECL logic family/ List the characteristics of the ECL.
3. (a) Implement the following Boolean function using4:1 MUX.
F(A, B, C, D)=Σm( 0,1,2,4,6,9,12,14).
(b) What is the necessity of the tri state buffer? Explain.
4. (a) What is ALU? Design a 8-bit ALU circuit using 74LS181 IC’s.
(b) Write a VHDL code for ALU chip.
5. (a) Explain the JK flip flop using NAND gates.
(b) Write a short note on mealy and Moore machines.
6. (a) Explain the operation of the 4-bit Johnson counter.
(b) With the help of the 2 shift registers design a4-bit serial adder.
7. (a) Design a 3 bit up/down counter by PLA.
(b)Explain how a 4x4 binary multiplier is implemented using 256x8 ROM.
8. Write a sort notes on
a. EPROM
b. Read and Write operations of DRAM.
*****
Set No: 4 R10
III B.Tech. I Semester Regular Examinations, November/December - 2012DIGITAL IC APPLICATIONS
(Electronics and Communication Engineering)
Time: 3 Hours Max Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
*****
1. Explain the terms with respect to CMOS logic
a. Noise margin
b. Logic levels
c. Transition time
d. Propagation delay.
2. (a) Explain the operation of transistor inverter with it’s transfer characteristics.
(b)Design a 2 input OR gate using ECL logic and verify the truth table.
3. (a) Design a 2-bit comparator using gates.
(b) Explain the n-bit parallel adder and write the VHDL code for a 8 bit ripple carry adder.
4. (a) Explain what is dual priority encoder? Write a VHDL code for the same.
(b) Write the design procedure for combinational circuit.
5. (a) Explain and design the asynchronous MOD-10 or decade counter.
(b) Write a short note on state assignment with an example.
6. (a)Explain the modes of operation of shift register?
(b) What are the applications of the shift registers.
7. (a) What is PAL? Explain how it differs with PLA.
(b) Implement the following multi Boolean function using 3x4x2 PLA.
F1(A,B,C)= Σm(0,1,3,4)
F2=(A,B,C)= Σm(1,2,3,5,7)
8. Write a short note on
a. DRAM timing
b. Internal structure of ROM.
*****
